SiSoftware Sandra Lite 歷史版本列表
更新時間：2023-08-08
更新細節：
What's new in this version:
CPU Multi-Media Benchmarks:
- AVX-iFMA(52): New 256-bit code path based on AVX512-iFMA(52) 512-bit for future arch (e.g. “Meteor Lake” MTL, “Arrow Lake” ARL). We saw +66% improvement as detailed in our AVX512-iFMA(52) Improvement for IceLake and TigerLake article.
- AVX512-FP16: New code path for Xeon processors that support AVX512-FP16. We expect +90% improvement over FP32 if precision loss in acceptable (e.g. zoomed out fractals).
- Note: Future FP16 code-paths will also be added to the other CPU benchmarks, however some parts may remain FP32 as the loss of precision would make the results useless. We have explored this in our GP-GPU article dealing with FP16 support: FP16 GP-GPU Image Processing Performance & Quality.
CPU Cryptogaphy Benchmarks:
- SHA2-512 HWA: Hardware-accelerated hashing SHA512 code-path – based on current SHA2-256 HWA. We expect ~3x (three times) better performance based on the SHA2 non-accelerated/HWA results.
- Future SM3-256 (China) HWA: Hardware-accelerated hashing SM3 code-path (China’s version of SHA hashing functions). We expect similar performance improvement to SHA HWA.
- Future SM4-128/256 (China) HWA: Hardware-accelerated block crypto SM4 code-path (China’s version of AES block crypto functions). We expect similar performance improvement to AES HWA.
- Note: We will default to “SM4 + SM3” benchmarks – rather than “AES + SHA” for both CPU & GP-GPU Cryptography benchmarks when “China” locale is detected as these algorithms are more likely to be used there.
- Note 2: ARM already includes SHA2-512, SM4, SM3 HWA (hardware acceleration extensions) in their high-end cores.
- Note 3: While AES & SHA are not going anywhere, there has been a shift to other crypto-algorithms (especially those that can encrypt/decrypt and hash/authenticate like “ChaCha20Poly1305” as famously used in WireGuard VPN) that are fast enough even without hardware acceleration!
All CPU Benchmarks – AVX10 Support:
- AVX10.2+ 256-bit future code paths (FP32, FP64 and FP16) for Hybrid architectures (e.g. “Meteor Lake” MTL, “Arrow Lake” ARL). Note both Core (P) and Atom (E) will run the same 256-bit width binary and not different widths
- AVX10.1+ 512-bit & AVX512 shared code path (FP32, FP64 and FP16) for Xeon architectures
- Possible AVX10.2+ 128-bit future code path for Atom/Other discrete architectures if required
- Note: in future Hybrid arch, Core (P) cores are likely to support 128/256-bit widths only. We don’t know (and we could not tell you) whether disabling Atom (E) cores will get the Core (P) to report 512-bit widths.
Hardware Support:
- Intel 14th gen Hybrid “Raptor Lake Refresh” RPL-S support
- Intel future gen Hybrid “Meteor Lake” (MTL-S/M/P/N), “Arrow Lake” (ARL-S/U), “Lunar Lake” (LNL-M) detection
- Intel future gen Xeon “Granite Rapids” SP/D detection
更新時間：2023-08-08
更新細節：
What's new in this version:
CPU Multi-Media Benchmarks:
- AVX-iFMA(52): New 256-bit code path based on AVX512-iFMA(52) 512-bit for future arch (e.g. “Meteor Lake” MTL, “Arrow Lake” ARL). We saw +66% improvement as detailed in our AVX512-iFMA(52) Improvement for IceLake and TigerLake article.
- AVX512-FP16: New code path for Xeon processors that support AVX512-FP16. We expect +90% improvement over FP32 if precision loss in acceptable (e.g. zoomed out fractals).
- Note: Future FP16 code-paths will also be added to the other CPU benchmarks, however some parts may remain FP32 as the loss of precision would make the results useless. We have explored this in our GP-GPU article dealing with FP16 support: FP16 GP-GPU Image Processing Performance & Quality.
CPU Cryptogaphy Benchmarks:
- SHA2-512 HWA: Hardware-accelerated hashing SHA512 code-path – based on current SHA2-256 HWA. We expect ~3x (three times) better performance based on the SHA2 non-accelerated/HWA results.
- Future SM3-256 (China) HWA: Hardware-accelerated hashing SM3 code-path (China’s version of SHA hashing functions). We expect similar performance improvement to SHA HWA.
- Future SM4-128/256 (China) HWA: Hardware-accelerated block crypto SM4 code-path (China’s version of AES block crypto functions). We expect similar performance improvement to AES HWA.
- Note: We will default to “SM4 + SM3” benchmarks – rather than “AES + SHA” for both CPU & GP-GPU Cryptography benchmarks when “China” locale is detected as these algorithms are more likely to be used there.
- Note 2: ARM already includes SHA2-512, SM4, SM3 HWA (hardware acceleration extensions) in their high-end cores.
- Note 3: While AES & SHA are not going anywhere, there has been a shift to other crypto-algorithms (especially those that can encrypt/decrypt and hash/authenticate like “ChaCha20Poly1305” as famously used in WireGuard VPN) that are fast enough even without hardware acceleration!
All CPU Benchmarks – AVX10 Support:
- AVX10.2+ 256-bit future code paths (FP32, FP64 and FP16) for Hybrid architectures (e.g. “Meteor Lake” MTL, “Arrow Lake” ARL). Note both Core (P) and Atom (E) will run the same 256-bit width binary and not different widths
- AVX10.1+ 512-bit & AVX512 shared code path (FP32, FP64 and FP16) for Xeon architectures
- Possible AVX10.2+ 128-bit future code path for Atom/Other discrete architectures if required
- Note: in future Hybrid arch, Core (P) cores are likely to support 128/256-bit widths only. We don’t know (and we could not tell you) whether disabling Atom (E) cores will get the Core (P) to report 512-bit widths.
Hardware Support:
- Intel 14th gen Hybrid “Raptor Lake Refresh” RPL-S support
- Intel future gen Hybrid “Meteor Lake” (MTL-S/M/P/N), “Arrow Lake” (ARL-S/U), “Lunar Lake” (LNL-M) detection
- Intel future gen Xeon “Granite Rapids” SP/D detection
更新時間：2023-08-08
更新細節：
更新時間：2023-04-02
更新細節：
What's new in this version:
Benchmarks, Hardware Support updates and fixes:
CPU / Platform Detection:
- Additional Intel Core 13 (RaptorLake) HX/H/P/U-Series support
Gp-Gpu Benchmarks:
- Updated CUDA SDK
更新時間：2022-12-16
更新細節：
What's new in this version:
Gp-GPU – CUDA:
- Updated to CUDA 11.8
- Support for 9.0 devices
Memory Detection:
- Intel XMP 3.0, AMD EXPO DDR5 detection missing in some instances
- Added support for more chipsets (both AMD and Intel)
更新時間：2022-11-19
更新細節：
What's new in this version:
Gp-GPU Performance:
- nVidia 4090 series FP16 validation failure (too low precision for image size)
- nVidia CUDA 90 / 89 support
Gp-Gpu Memory Bandwidth:
- Corrected DirectX Compute (11/12) bandwidths with some internal graphics
Memory Detection:
- Intel XMP 30, AMD EXPO DDR5 detection missing in some instances
- Jedec, Intel XMP 20 DDR4 write timings if provided by newer standard revision
- Corrected timings (tRP, tRAS) for some Intel ADL/RPL systems
- Missing memory timings for some mobile Intel ADP-P/U systems
- Added support for more chipsets (both AMD and Intel)
更新時間：2022-10-18
更新細節：
更新時間：2022-09-07
更新細節：
What's new in this version:
- Parallelism: All CPU/Memory Benchmarks
- Additional “Multi-Threaded big/P Cores Only” aka only using threads running on big/P cores (SMT)
- Note that as (current) LITTLE/E Atom cores do not support SMT, there is no corresponding option for them yet
- Cache & Memory Bandwidth Benchmark
Improved/fixed hybrid bandwidth workload allocation when all cores are used, e.g. on Intel 12600K:
- Memory Bandwidth Improvement: 49GB/s to 56GB/s: +14% improvement (float AVX2/buffered)
- L1D Cache Bandwidth – not affected
- L2 Caches Bandwidth fix: 145GB/s to 836GB/s
- L3 Cache Bandwidth fix: 56GB/s to 452GB/s
- Cluster Performance Contribution: All CPU/Memory Benchmarks
- It is the sum of the performance of all cores in each cluster
Reveals how much the big/P & LITTLE/E core clusters have contributed compute power wise to each benchmark score in percent, e.g. on Intel 12600K – CPU Arithmetic Benchmark:
- 80% big/P Cluster – 20% LITTLE/E Atom cluster
- Review showing these measurements: big/LITTLE cores Performance Analysis – AlderLake to RaptorLake
- Note this also works on Arm64 big.LITTLE or DynamiQ SoCs
- Core Performance Ratio: All CPU/Memory Benchmarks
- It is the ratio of the big/P Core vs. LITTLE/E core performance
Reveals just how much more performant the big/P Cores are vs. the LITTLE/E cores, e.g. on Intel 12600K – CPU Arithmetic Benchmark:
- 2.15x big/P Core – 1.x LITTLE/E Atom core
- Review showing these measurements: big/LITTLE cores Performance Analysis – AlderLake to RaptorLake
- Note this also works on Arm64 big.LITTLE or DynamiQ SoCs
Future Hardware Support:
- Additional AMD Ryzen 7000 (Zen4) support
- Enabled DDR5 SPD (Hub, PMIC, TS) AMD information
- Additional Intel Sapphire Rapids (SRP-X/EX) support
- Preliminary Intel MeteorLake (MTL) support
- Preliminary Intel Granite Rapids (GRP-EX) support
- Enabled DDR5 SPD (Hub, PMIC, TS) Intel information
更新時間：2022-07-28
更新細節：
更新時間：2022-07-22
更新細節：
What's new in this version:
- Benchmarks, Hardware Support updates and fixes
CUDA GP-GPU Benchmarks:
- Updated to CUDA SDK 11.8 with nVidia Ada support [GeForce RTX 4090, etc.]
Memory Bandwidth Benchmark:
- 3-5% bandwidth increase due to L1D block/prefetch optimisations [e.g. AVX512 AMD Zen4, Intel ICL-SP, future arch.]
Memory Latency Benchmark:
- “In-Page Random” memory access latency pattern – additional TLB ranges randomisation in addition to the randomisation within each TLB range
- Benchmark now fails (does not run at all) if TLB information cannot be detected, e.g. CPU does not report it.
- This change affects both Data and Code latencies
- Note that the other tests “Full Random” and “Sequential” memory access patterns – are *not* affected – as the pattern is not affected by TLB data
- It is always recommended to use “2MB/large” pages rather than “4kB/normal” pages in order to minimise “TLB miss” penalties which is the reason for the “in-page random” test. Please see How to enable large/huge memory pages in Windows.
Cryptography Benchmark:
- 3-5% bandwidth increase due to L1D block/prefetch optimisations [e.g. AVX512-VAES AMD Zen4, Intel ICL-SP, future arch.]
Client (GUI):
- Light/Dark-mode colour optimisations